instruction n. 1.教育,教導(dǎo)。 2.教訓(xùn),教誨。 3.〔 pl.〕 指令,訓(xùn)令,指示,細(xì)目。 give sb. instructions to do sth. 命令某人做什么。 an instruction book 說明書。 maintenance instructions 維護(hù)說明。 operating instructions 業(yè)務(wù)[工作]須知,操作規(guī)程。 ask for instruction 請示。 give instruction in 教授。 give instructions to 訓(xùn)令。 receive in instruction 接受指導(dǎo)。
If there is no instruction cache , this subroutine may be a no - op 如果在你的目標(biāo)機(jī)上,沒有指令緩存,則可能不做任何操作。
Instruction to invalidate the instruction cache line that will contain the modified instruction 指令,使將要存放修改后指令的指令高速緩存行無效。
On sparc and sparclite only , write this subroutine to flush the instruction cache , if any , on your target machine 只在sparc和sparclite平臺上,這一功能調(diào)用用來刷新指令緩存。
It is a risc microprocessor , has a six - stage pipeline , with separated data cache and instruction cache 銀河ts - 1采用典型的risc結(jié)構(gòu),六級流水線,具有獨(dú)立的指令cache和數(shù)據(jù)cache 。
In order to gain more performance improvement 8k data cache and 8k instruction cache are used in ck510 這些改進(jìn)使c - core性能大大超過m - core 。整數(shù)運(yùn)算能力是嵌入式cpu中重要的性能指標(biāo)。
The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed 指令讀取器產(chǎn)生讀取位址以供快取記憶體讀取快取區(qū)塊內(nèi)的指令。
On target machines that have instruction caches , gdb requires this function to make certain that the state of your program is stable 在有指令緩存的目標(biāo)機(jī)上, gdb需要這一函數(shù),以確定你的程序的狀態(tài)是穩(wěn)定的。
An instruction cache miss will occur when fetching this instruction , resulting in the fetching of the modified instruction from storage 當(dāng)取這個(gè)指令時(shí)會發(fā)生指令高速緩存失敗,結(jié)果就會從存儲器中取得修改后的指令。
And in fact , the problem is exacerbated by the fact that a media app pushes data through the data cache much faster than a static app pushes code through the instruction cache 事實(shí)上,這是由于動態(tài)媒體程序需要以遠(yuǎn)遠(yuǎn)高于靜態(tài)程序填充指令的速度來填充數(shù)據(jù)。
This paper presents the logic circuit design of ccu for lx - 1164 cpu chip , for ccu , data and instructions are stored in separate data and instruction caches 本人有幸在夏宏博士的指導(dǎo)下參加這一工程,承擔(dān)lx ? 1164cpu的高速緩存控制器( ccu )的邏輯設(shè)計(jì)和功能仿真。